IC Layout Designer - Analog & Mixed-Signal

Avicena Tech

Sunnyvale (CA)

On-site

USD 120,000 - 180,000

Full time

14 days+

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Job summary

Avicena Tech in Sunnyvale, CA is seeking an experienced IC Layout Designer to support the physical layout of analog, mixed-signal, and high-speed ICs. You will translate schematics into manufacturable layouts, ensuring matching, parasitic, reliability and manufacturability per foundry rules.

Candidates should have CADENCE Virtuoso layout experience, DRC/LVS tooling (Calibre/ Pegasus/ Assura), and a strong grasp of CMOS layout techniques, device matching, floorplanning, and parasitic extraction

Qualifications

Associate or bachelor’s degree in electrical engineering, microelectronics, or related field.
Experience with IC layout tools such as Cadence Virtuoso Layout Suite.
Solid understanding of CMOS device layout and process layers.
Experience running and debugging DRC/LVS using Calibre, Assura, Pegasus, or similar.
Ability to read and understand circuit schematics.
Strong attention to detail and ability to follow layout guidelines.
Knowledge of parasitic effects, device matching, shielding, and signal integrity.
Good communication skills and ability to work with circuit designers.

Responsibilities

Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.
Work from circuit schematics to create clean, compact, and manufacturable layouts.
Layout devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.
Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.
Run and debug physical verification checks including DRC, LVS, ERC, antenna checks, density checks, and reliability checks.
Perform parasitic extraction and work with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.
Support layout floorplanning, block-level integration, and top-level chip assembly.
Follow foundry design rules and process-specific layout guidelines.
Work with design engineers to optimize layout for performance, area, power, yield, and reliability.
Prepare layout databases for tapeout and support final verification signoff.