Senior Digital IC Layout & Verification Engineer

Snapchat, Inc.; Washington (District of Columbia); Presencial; USD 164.000 - 259.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

RSU equity

Paid parental leave

Comprehensive medical coverage

Descripción de la vacante

Snap Inc seeks a Custom IC Layout Engineer to join the MicroDisplay Electronics at SPECS. You will design analog and mixed-signal ICs for AR, collaborating with digital and analog teams, and craft layouts to meet area, performance, and power goals.

Proficiency in Cadence Virtuoso and Mentor Calibre is required, with 5+ years of relevant experience. You will contribute to parasitic extraction, tape-out readiness, and design reviews in a fast-paced environment.

Formación

• BSEE or equivalent; 5+ years in custom IC layout.
• Experience with SRAM, IPs like PLLs, Bandgaps, ADCs/DACs.
• Proficient in Cadence Virtuoso and Calibre for layout and verification.

Responsabilidades

• Perform cell and block layout for analog/mixed-signal circuits.
• Support IC floor planning and place & route of full-chip designs.
• Create design documentation and perform parasitic extraction.

Conocimientos

Analog/mixed-signal design

Layout verification

Team collaboration

Scripting (TCL, Python)

Educación

BSEE or equivalent

Herramientas

Cadence Virtuoso

Mentor Calibre

Linux scripting

Descripción del empleo

Snap Inc seeks a Custom IC Layout Engineer to join the MicroDisplay Electronics at SPECS. You will design analog and mixed-signal ICs for AR, collaborating with digital and analog teams, and craft layouts to meet area, performance, and power goals.

Proficiency in Cadence Virtuoso and Mentor Calibre is required, with 5+ years of relevant experience. You will contribute to parasitic extraction, tape-out readiness, and design reviews in a fast-paced environment.