Senior IC Layout Designer: Tapeout-Ready Silicon

Encore Semi, Inc.

San Diego (CA)

On-site

USD 90,000 - 110,000

Full time

13 days ago

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Benefits offered by this job

PTO 15 days
Holidays 10 days
Medical benefits
Dental & Vision
Life Insurance
401k
Tuition reimbursement

Job summary

Encore Semi, Inc. seeks a Senior IC Layout Designer to join our semiconductor team, delivering high-quality digital and mixed-signal layouts for production silicon.

You will translate schematics into robust layouts, perform floorplanning, placement, routing, and optimization for PPA, and collaborate with IC designers, verification, and process teams to ensure manufacturability and reliable tapeouts. The role offers an hourly compensation of $65–$80 with comprehensive benefits and bonus

Qualifications

  • 7+ years of hands-on IC layout design experience.
  • Experience with Cadence Virtuoso and Synopsys tools.
  • Strong CMOS process knowledge and physical design concepts.
  • Proven experience achieving DRC/LVS closure.
  • Knowledge of parasitics, signal integrity, timing and layout optimization.

Responsibilities

  • Develop block-level and full-chip physical layouts for digital/mixed-signal ICs.
  • Translate schematics into high-quality layout implementations.
  • Perform floorplanning, placement, routing, and layout refinement for PPA.
  • Drive DRC, LVS, and ERC closure and debugging complex issues.
  • Analyze layouts for parasitics, signal integrity, timing, manufacturability.
  • Collaborate with circuit designers and foundries during tapeout and release.

Skills

IC layout design
Cross-functional teamwork
Parasitics and timing
Layout optimization
CMOS process knowledge

Tools

Cadence Virtuoso
Synopsys tools
Parasitic extraction
SKILL
Python
TCL

Job description

Encore Semi, Inc. seeks a Senior IC Layout Designer to join our semiconductor team, delivering high-quality digital and mixed-signal layouts for production silicon.

You will translate schematics into robust layouts, perform floorplanning, placement, routing, and optimization for PPA, and collaborate with IC designers, verification, and process teams to ensure manufacturability and reliable tapeouts. The role offers an hourly compensation of $65–$80 with comprehensive benefits and bonus

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