Senior IC Layout Engineer – Next-Gen Silicon & PPA

Encore Semi, Inc.; Sunnyvale (CA); On-site; USD 90,000 - 110,000; Full time

Benefits offered by this job

15 days PTO

10 holidays

Medical benefits

Dental & Vision

Life Insurance

401k

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking a Senior IC Layout Designer to join our semiconductor engineering team. You will develop complex digital and mixed-signal layouts, translating schematics into production-ready silicon across advanced nodes.

You will collaborate with IC designers, verification teams, and process groups to optimize performance, power, area, and manufacturability, while mentoring junior engineers and contributing to layout automation and flows.

Qualifications

• 7+ years of hands-on IC layout design experience in advanced semiconductor technologies.
• Deep understanding of CMOS process technology and physical design concepts.
• Proven experience achieving DRC/LVS closure and resolving complex verification challenges.
• Strong knowledge of parasitic extraction, signal integrity, and timing impact.

Responsibilities

• Develop block-level and full-chip physical layouts for complex digital and mixed-signal IC designs.
• Translate schematics into layout implementations while preserving design intent.
• Perform floorplanning, placement, routing, optimization, and layout refinement for PPA.
• Drive DRC, LVS, and ERC closure; debug layout and verification issues.
• Collaborate with circuit designers, verification teams, and foundry partners during tapeout.
• Mentor junior layout engineers and contribute technical expertise.

Skills

IC layout design

Cadence Virtuoso

Synopsys tools

CMOS process knowledge

DRC/LVS/ERC closure

Parasitic extraction

Timing analysis

Cross-functional teamwork

Tools

Cadence Virtuoso

Synopsys tools

SKILL

Python

TCL

Job description

Encore Semi, Inc. is seeking a Senior IC Layout Designer to join our semiconductor engineering team. You will develop complex digital and mixed-signal layouts, translating schematics into production-ready silicon across advanced nodes.

You will collaborate with IC designers, verification teams, and process groups to optimize performance, power, area, and manufacturability, while mentoring junior engineers and contributing to layout automation and flows.