Senior Hybrid Design Verification Engineer

Socionext US; Milpitas (CA); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Socionext US is seeking a Design Verification Engineer to drive verification for ASIC projects. The role emphasizes hands-on development of UVM-based testbenches, regression suites, and coverage reporting within a global engineering environment.

The candidate should bring 5–10+ years in ASIC verification, strong SystemVerilog/Verilog knowledge, debugging skills, and experience with ARMv8/9 and memory architectures. Hybrid work arrangements are supported.

Qualifications

• BS or MS in Computer Science or Electrical Engineering.
• 5–10+ years of ASIC verification experience.
• Proficient with UVM and SystemVerilog.

Responsibilities

• Verify ASIC designs using UVM testbenches and SystemVerilog.
• Develop and maintain regression suites and coverage metrics.
• Collaborate with design and software teams to debug issues.
• Lead verification efforts on silicon projects.

Skills

UVM

SystemVerilog

Verilog

ARMv8/9

Memory architecture

Debugging skills

Scripting

C-based tests

Code coverage

Education

BS/MS in Computer Science or Electrical Engineering

Tools

Verilog simulators

Formality

Emulation

Job description

Socionext US is seeking a Design Verification Engineer to drive verification for ASIC projects. The role emphasizes hands-on development of UVM-based testbenches, regression suites, and coverage reporting within a global engineering environment.

The candidate should bring 5–10+ years in ASIC verification, strong SystemVerilog/Verilog knowledge, debugging skills, and experience with ARMv8/9 and memory architectures. Hybrid work arrangements are supported.