Senior Hardware Verification Engineer - Testbenches & UVM

Semiconductor Engineering; Santa Clara, Northern (CA, KY); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Semiconductor Engineering is seeking a seasoned Design Verification designer who specializes in building testbenches and writing test sequences for complex IPs across SoCs.

You will create configurable test plans, write UVM/SystemVerilog code, and collaborate with software and design teams on verification, coverage, and failure debugging. This role offers the chance to influence our technology portfolio and work with cutting-edge silicon.

Qualifications

• Experience designing testbenches for complex IPs.
• Ability to write and debug test sequences in SystemVerilog/UVM.
• Strong understanding of verification methodologies for IPs and SoCs.

Responsibilities

• Create test plans for configurable IPs used to interconnect components across SoCs, chiplets, or multi-chiplet systems.
• Write UVM/SystemVerilog code to implement test plans, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.
• Work with design teams on test plans, failure debugging, and coverage.

Job description

Semiconductor Engineering is seeking a seasoned Design Verification designer who specializes in building testbenches and writing test sequences for complex IPs across SoCs.

You will create configurable test plans, write UVM/SystemVerilog code, and collaborate with software and design teams on verification, coverage, and failure debugging. This role offers the chance to influence our technology portfolio and work with cutting-edge silicon.