Senior SOC Design Verification Engineer - Hybrid

Advanced Micro Devices; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose, CA is seeking an adaptive design verification engineer to join our SOC team. You will develop and maintain tests to drive functional and performance verification for core and SOC level, collaborating across sites.

The role emphasizes strong coding in Verilog/SystemVerilog, UVM, C/C++, and scripting (Perl/Python). You will contribute to testbench components and help close coverage metrics while enabling next-generation IP delivery.

Qualifications

• Bachelor's or Master's degree in computer or electrical engineering.
• Strong understanding of SOC architecture and CPU/DSP processors.
• Proficient in Verilog/SystemVerilog, UVM, and C/C++ with scripting in Perl/Python.

Responsibilities

• Develop and maintain tests for functional and performance verification at core and SOC levels.
• Build testbench components to support next-generation IP.
• Maintain and improve test libraries for IP-level testing.
• Close verification quality metrics such as pass rates, code coverage, and functional coverage.
• Provide technical support to other teams.

Skills

SOC architecture

CPU/DSP processors

Verilog/SystemVerilog

UVM

C/C++

Perl/Python scripting

Education

Bachelors or Masters in Computer Engineering/Electrical Engineering

Job description

AMD in San Jose, CA is seeking an adaptive design verification engineer to join our SOC team. You will develop and maintain tests to drive functional and performance verification for core and SOC level, collaborating across sites.

The role emphasizes strong coding in Verilog/SystemVerilog, UVM, C/C++, and scripting (Perl/Python). You will contribute to testbench components and help close coverage metrics while enabling next-generation IP delivery.