Senior High-Speed PCB Layout Engineer

Hewlett Packard Enterprise; Chippewa Falls (WI); On-site; USD 96,000 - 221,000; Full time

Job summary

Hewlett Packard Enterprise seeks a seasoned PCB Layout Engineer to design complex multilayer PCBs for high-performance systems. You will lay out boards using Cadence Allegro, ensure signal integrity, EMI compliance, and manufacturability, then drive releases to production.

You will collaborate with electrical, mechanical, and SI/PI engineers across geographies to meet performance targets, assist in design decisions, and support advanced cooling and next-gen interfaces like PCIe Gen4+/DDR4.

Qualifications

• Associate degree or equivalent technical degree with 10+ years of experience laying out complex, multilayer, high-speed PCBs.
• Bachelor’s degree in Electrical Engineering or equivalent with 4+ years of experience laying out complex, multilayer, high-speed PCBs.
• Advanced knowledge of Cadence Allegro PCB Editor required.
• Advanced knowledge of PCB design guidelines and design constraints.
• Experience laying out boards with DDR4 or newer, PCIe Gen 4 or newer, high-speed SerDes, Ethernet, I²C, SPI, and similar interfaces.
• Experience with high-speed routing techniques, such as microvias, blind and buried vias, and backdrilling.

Responsibilities

• Design printed circuit board layouts using CAD software in line with circuit-performance, SI, EMI, mechanics, thermal, and manufacturing specs.
• Read schematics and guidelines to complete PCB layouts per requirements.
• Determine PCB design approaches and parameters.
• Influence design decisions to address system-performance issues in PCB layouts.

Skills

PCB Layout

Cadence Allegro PCB Editor

High-speed design

Signal Integrity

EMI/EMC knowledge

DFM/DFT

DDR4/PCIe SerDes

Open Compute Project familiarity

Measurement/Testing

Education

Associate degree or equivalent technical degree

Bachelor’s degree in Electrical Engineering or equivalent

Tools

Cadence Allegro PCB Editor

ECAD software

Job description

Hewlett Packard Enterprise seeks a seasoned PCB Layout Engineer to design complex multilayer PCBs for high-performance systems. You will lay out boards using Cadence Allegro, ensure signal integrity, EMI compliance, and manufacturability, then drive releases to production.

You will collaborate with electrical, mechanical, and SI/PI engineers across geographies to meet performance targets, assist in design decisions, and support advanced cooling and next-gen interfaces like PCIe Gen4+/DDR4.