Senior PCB Layout Engineer – High-Speed Server/Datacenter

HCLTech; Menlo Park (CA); On-site; USD 88,000 - 148,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) retirement plan

10 days paid time off

10 paid holidays

Job summary

HCLTech is seeking an experienced PCB Layout Engineer in Menlo Park, CA, to lead complex server and data center board layouts using Cadence Allegro. You will own end-to-end layout activities for high-density designs featuring DDR5, PCIe Gen5/Gen6, and high-speed interfaces.

Collaborate with electrical and mechanical teams on constraints, routing, power integrity, and manufacturability while delivering robust designs and documentation for prototype and production builds.

Qualifications

• 8+ years of PCB layout and CAD design experience.
• Expert-level proficiency with Cadence Allegro.
• Hands-on expertise with HDI, blind/buried vias, and microvia technologies.
• Proven experience designing boards based on SoCs, Microprocessors, FPGAs, or Intel platforms.

Responsibilities

• Own end-to-end PCB layout activities for complex, high-density server and datacenter hardware designs.
• Perform high-speed PCB layout for interfaces including DDR4/DDR5, LPDDR5, PCIe Gen5/Gen6, HBM, USB, and other high-speed buses.
• Develop and enforce layout constraints related to controlled impedance, length matching, signal integrity, power integrity, and crosstalk mitigation.
• Collaborate closely with electrical engineers to review schematics, optimize component placement, power distribution networks, and routing strategies.
• Partner with mechanical teams to resolve board outline, stack-up, thermal, connector placement, and enclosure constraints.
• Execute HDI PCB designs utilizing blind, buried, and microvia technologies.
• Drive DFM, DFA, and DFT reviews with PCB fabricators and contract manufacturers to ensure manufacturability, reliability, and yield.
• Maintain PCB libraries, stack-up definitions, design standards, and layout best practices.
• Support prototype and production builds through layout documentation, net tracing, design analysis, and engineering change implementation.

Skills

HDI vias

SoCs/FPGA experience

Intel platforms

Tools

Cadence Allegro

Job description

HCLTech is seeking an experienced PCB Layout Engineer in Menlo Park, CA, to lead complex server and data center board layouts using Cadence Allegro. You will own end-to-end layout activities for high-density designs featuring DDR5, PCIe Gen5/Gen6, and high-speed interfaces.

Collaborate with electrical and mechanical teams on constraints, routing, power integrity, and manufacturability while delivering robust designs and documentation for prototype and production builds.