Senior High-Speed PCB Designer for PCIe Gen 6 & DDR5 HDI

CBL Solutions; Menlo Park (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

CBL Solutions in Menlo Park, CA, seeks an experienced PCB Layout Engineer to own end-to-end layout for high-density server-board designs and high-speed interfaces, using Cadence Allegro. You will drive impedance control, length matching, and crosstalk mitigation on memory and PCIe interfaces (Gen5/6).

The role collaborates with EEs and ME engineers to meet manufacturability and reliability standards. Ideal candidates bring 5+ years of CAD experience, HDI microvia know-how, and a track record in

Qualifications

• Own end-to-end PCB layout for complex, high-density designs used in data center server boards.
• Perform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigation.
• Develop and enforce layout design rules for High-speed digital, analog, mixed-signal, and power domains within tightly constrained wearable form factors.
• Collaborate with electrical engineers to review schematics and provide layout-driven feedback on component placement, power distribution network design, and signal routing strategies.
• Partner with mechanical engineers to resolve physical constraints including board outline, connector placement, thermal management, and stack-up definition.
• Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure layouts meet yield and reliability targets.
• Maintain and improve PCB design standards, layer stack-up libraries, and footprint libraries to support scalable development across multiple hardware programs.
• Support by providing layout documentation, net tracing support, and design revision analysis for prototype and production boards.

Responsibilities

• Own end-to-end PCB layout for complex, high-density designs used in data center server boards.
• Perform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigation.
• Develop and enforce layout design rules for High-speed digital, analog, mixed-signal, and power domains within tightly constrained wearable form factors.
• Collaborate with electrical engineers to review schematics and provide layout-driven feedback on component placement, power distribution network design, and signal routing strategies.
• Partner with mechanical engineers to resolve physical constraints including board outline, connector placement, thermal management, and stack-up definition.
• Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure layouts meet yield and reliability targets.
• Maintain and improve PCB design standards, layer stack-up libraries, and footprint libraries to support scalable development across multiple hardware programs.
• Support by providing layout documentation, net tracing support, and design revision analysis for prototype and production boards.

Skills

Allegro PCB

CAD software (2D/3D)

5+ years CAD experience

HDI microvia

SoC/FPGA PCB design

High-density / high-speed PCB design

Constraint Editor (CES) & DFA/DFM/DFT

Communication skills

Tools

Cadence Allegro Layout tool 23.1+

Job description

CBL Solutions in Menlo Park, CA, seeks an experienced PCB Layout Engineer to own end-to-end layout for high-density server-board designs and high-speed interfaces, using Cadence Allegro. You will drive impedance control, length matching, and crosstalk mitigation on memory and PCIe interfaces (Gen5/6).

The role collaborates with EEs and ME engineers to meet manufacturability and reliability standards. Ideal candidates bring 5+ years of CAD experience, HDI microvia know-how, and a track record in