Senior High-Speed PCB Layout Engineer – DDR5/PCIe Gen5/6

HCLTech; Menlo Park (CA); On-site; USD 78,000 - 148,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Life insurance

AD&D insurance

Disability insurance

Employee assistance program

401(k) retirement plan

Paid time off

Paid holidays

Job summary

HCLTech is seeking a highly talented PCB Design Layout Engineer in Menlo Park, CA to own end-to-end layouts for complex data center server boards. You will drive high-speed layouts and collaborate across EE, ME teams to ensure optimal placement, routing, and manufacturability.

The role demands 10+ years CAD experience with Cadence Allegro, HDI via expertise, and proficiency in high-density, high-speed memory designs (DDR5/LPDDR5) and PCIe Gen5/6. Equal opportunity employer.

Qualifications

• 10+ years of CAD experience focusing on high-density PCB layouts.
• Proficiency with Cadence Allegro Layout tool 23.1+ is mandatory.
• Hands-on experience with HDI micro via technology (Blind/Buried).
• Experience with high-density/ high-speed memory designs (DDR5/LPDDR5) and PCIe Gen5/6.

Responsibilities

• Own end-to-end PCB layout for complex, high-density designs used in data center server boards.
• Perform high-speed digital layout for interfaces like HBM, DDR4/5, PCIe Gen 5/6, USB 3.2+, with controlled impedance and length matching.
• Develop layout design rules for high-speed digital, analog, mixed-signal, and power domains.
• Collaborate with electrical engineers to review schematics and provide layout-driven feedback.
• Partner with mechanical engineers on board outline, connectors, thermal management, and stack-up.
• Drive DFM/DFT reviews with manufacturers to meet yield and reliability targets.
• Maintain PCB design standards, layer stack-up and footprint libraries.
• Provide layout documentation, net tracing support, and revision analysis for prototypes and production boards.

Skills

Allegro PCB

Cadence CAD (2D/3D)

10+ years CAD

HDI via technology

SoC/FPGA PCB design

CES constraints

DFT/DFM/DFT

Communication skills

Tools

Cadence Allegro Layout 23.1+

3D CAD tools

Job description

HCLTech is seeking a highly talented PCB Design Layout Engineer in Menlo Park, CA to own end-to-end layouts for complex data center server boards. You will drive high-speed layouts and collaborate across EE, ME teams to ensure optimal placement, routing, and manufacturability.

The role demands 10+ years CAD experience with Cadence Allegro, HDI via expertise, and proficiency in high-density, high-speed memory designs (DDR5/LPDDR5) and PCIe Gen5/6. Equal opportunity employer.