Senior High-Speed Layout Architect for Memory Interfaces

1000 Micron Technology, Inc.; San Jose (CA); On-site; USD 202,000 - 344,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Bonus and equity

Paid time off and holidays

Job summary

Micron Technology, Inc. in California seeks a Senior/Principal Layout Engineer to drive pathfinding and architecture exploration for next‑gen memory modules and form factors. You will lead layout-driven decisions influencing DDR/LPDDR interfaces, SI/PI budgets, and advanced PCB technologies.

You will mentor engineers, collaborate with SI/PI teams, and help define design envelopes for 10–20+ Gb/s signaling while shaping layout methodologies across programs.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8-15+ years of experience in high-speed PCB layout and complex designs.
• Deep expertise in DDR/LPDDR memory interfaces or similar ultra-high-speed parallel interfaces.
• Strong signal integrity and power integrity knowledge with practical design experience.
• Ability to influence architecture decisions through physical design constraints.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects.
• Evaluate form factor, routing topology, and pinout tradeoffs to meet bandwidth targets.
• Define feasible design envelopes including routing complexity and via strategy.
• Collaborate with SI/PI teams to co-optimize channel topology and return-path design.
• Define and influence SI/PI budgets at the module level.
• Drive adoption of next-generation PCB technologies (HDI, via-in-pad, etc.).
• Develop layout methodologies and constraints for >10-20+ Gb/s signaling.
• Mentor junior engineers and propagate layout best practices.

Skills

High-speed layout

Signal integrity

Power integrity

Memory interfaces

Cross-functional collaboration

AI tools

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Allegro

OrCAD

Job description

Micron Technology, Inc. in California seeks a Senior/Principal Layout Engineer to drive pathfinding and architecture exploration for next‑gen memory modules and form factors. You will lead layout-driven decisions influencing DDR/LPDDR interfaces, SI/PI budgets, and advanced PCB technologies.

You will mentor engineers, collaborate with SI/PI teams, and help define design envelopes for 10–20+ Gb/s signaling while shaping layout methodologies across programs.