Senior HBM Design Verification Engineer for AI/ML

Micron Technology, Inc.; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Health benefits

Dental & vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Richardson, TX is seeking a Senior Design Verification Engineer to verify high‑density DRAM and HBM designs across full‑chip and block levels, and to develop verification plans, testbenches, and regressions in collaboration with global design teams.

The ideal candidate has 5–7+ years in mixed‑signal and digital verification, SystemVerilog (SVA), experience with HSPICE/Verilog‑HDL/FINESIM, and Python or Perl for automation.

Qualifications

• 5–7+ years of experience in mixed‑signal and/or digital verification methodologies.
• Solid understanding of CMOS circuit design fundamentals.
• Proficiency in SystemVerilog (or equivalent), including assertions (SVA).
• Experience with analog and digital simulation tools such as HSPICE, Verilog‑HDL, and FINESIM.
• Proficiency in Python or Perl to support verification automation.

Responsibilities

• Evaluate full‑chip and block‑level HBM and DRAM circuit designs for functional correctness and performance.
• Develop verification plans from functional specs with architects and design teams.
• Create, enhance, and maintain verification environments, testbenches, test vectors, and regressions.
• Increase functional coverage across DRAM architectures and features using verification tools.
• Debug design issues, perform root‑cause analysis, track bugs, and drive coverage and closure.
• Collaborate with global design, verification, and product teams to ensure project success.

Skills

SystemVerilog

Assertions (SVA)

Mixed-signal verification

Digital verification

Debugging

Python/Perl scripting

Technical leadership

AI-enabled verification tools

Education

B.S. in Electrical or Computer Engineering

Tools

HSPICE

Verilog-HDL

FINESIM

Job description

Micron Technology, Inc. in Richardson, TX is seeking a Senior Design Verification Engineer to verify high‑density DRAM and HBM designs across full‑chip and block levels, and to develop verification plans, testbenches, and regressions in collaboration with global design teams.

The ideal candidate has 5–7+ years in mixed‑signal and digital verification, SystemVerilog (SVA), experience with HSPICE/Verilog‑HDL/FINESIM, and Python or Perl for automation.