Senior HBM Design Engineer, High-Speed Memory & ASIC

Micron; Richardson (TX); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Vision coverage

Paid time off

Paid holidays

Paid family leave

Job summary

Micron Technology is seeking a seasoned memory design engineer to craft and analyze advanced DRAM circuitry, from data paths to core arrays, working with global teams across design, verification, and manufacturing. You will simulate, optimize, and floor plan to deliver low-power, high-performance memory solutions.

The role emphasizes MBIST-based validation, RTL synthesis, and timing/latency control in next-generation memory products, with collaborations spanning Product Engineering, Test,

Qualifications

• High-speed memory design on data paths from I/O interface to core array.
• Power domain network analysis.
• Memory test architectures MBIST and production silicon validation.
• Digital design methodologies including RTL design, synthesis, and physical implementation.
• ASIC design development using digital design.
• Memory core timing, latency control, and signal integrity considerations in advanced designs.

Responsibilities

• Design and analyze digital/analogue circuits for memory products.
• Simulate, optimize, and floor plan DRAM circuits.
• Collaborate with global design and verification teams and support Product Engineering, Test, Process Integration, Assembly, and Marketing.
• Develop end-to-end processes to optimize power, performance, and cost.

Skills

High-speed memory design

Power domain analysis

Memory test architectures MBIST

Digital design RTL

ASIC design development

Memory core timing and latency

Education

Master’s degree in Electrical Engineering or related field

Job description

Micron Technology is seeking a seasoned memory design engineer to craft and analyze advanced DRAM circuitry, from data paths to core arrays, working with global teams across design, verification, and manufacturing. You will simulate, optimize, and floor plan to deliver low-power, high-performance memory solutions.

The role emphasizes MBIST-based validation, RTL synthesis, and timing/latency control in next-generation memory products, with collaborations spanning Product Engineering, Test,