Senior Hardware Design Engineer

IC Resources; United States; Hybrid; USD 110,000 - 190,000; Full time

Benefits offered by this job

Stock options

401k with company match

Medical coverage

Dental coverage

Performance bonus

Job summary

IC Resources is seeking a Senior Hardware Design Engineer with extensive RTL design experience to translate requirements into micro architectures for ASIC and FPGA targets. You will build testbenches, bring up designs on FPGA platforms, and manage the full design lifecycle from architecture through verification and optimization.

The role emphasizes strong timing/resource optimization, power management, and proficiency with EDA tools.

Qualifications

• Extensive RTL design experience with Verilog/SystemVerilog for complex ASIC/FPGA
• Strong timing/resource optimization for high throughput
• Experience with power management, synthesis and timing closure
• Proficiency with EDA tools for simulation and synthesis
• Strong technical documentation skills including specs and verification plans

Responsibilities

• Translate requirements into micro architectures ready for RTL implementation
• Develop ASIC and FPGA designs including testbenches
• Bring up designs on FPGA platforms for validation
• Own full design lifecycle from micro architecture to verification and optimization
• Contribute to design standards as the team scales

Skills

RTL design

Verilog/SystemVerilog

ASIC/FPGA

Timing optimization

Power management

Synthesis and timing closure

EDA tools

Documentation

Tools

Synopsys

Cadence

UVM

C++/SystemC

AMD FPGA tools

Job description

Now Hiring: Senior Hardware Design Engineers

Satellite or space experience is not required for this role. We are looking for exceptional RTL designers.

My client develops advanced physical layer IP for next generation wireless and satellite communications. Their technology is already deployed in live satellite networks, and with demand continuing to grow, they are expanding their hardware engineering team.

Key Responsibilities:

• Collaborate with algorithm and system architecture teams to translate requirements into micro architectures ready for RTL implementation
• Develop designs for both ASIC and FPGA targets, including building testbenches
• Bring up designs on current FPGA platforms for validation and integration testing
• Own the full design lifecycle, from micro architecture through verification, physical implementation and optimization
• Contribute to engineering practices and design standards as the team scales

Required Qualifications:

• Extensive hands on RTL design experience (Verilog/SystemVerilog) on complex ASIC or FPGA products
• Proven record of delivering digital designs with strong timing and resource optimization for high throughput applications
• Experience with power management, synthesis and timing closure
• Advanced proficiency with EDA tools for simulation and synthesis
• Strong technical documentation skills, including specifications, user guides and verification plans

Preferred Qualifications:

• Communications signal processing (error correction, equalization, channel estimation, beamforming)
• UVM verification
• C++ or SystemC for design modeling
• High speed interfaces such as PCIe or JESD
• Python or other scripting languages
• AMD FPGA toolchains or ASIC backend EDA tools

Location: Hybrid on the West Coast, or remote anywhere in the US

Compensation and Benefits: Competitive base salary, company wide performance bonus, stock options, 401k with company match, and medical and dental coverage