Senior Design Engineer

The Judge Group; United States; Remote; USD 83,000 - 138,000; Full time

Benefits offered by this job

Medical, Dental and Vision Insurance

Job summary

The Judge Group is seeking a Sr. Design Engineer with a strong background in ASIC and FPGA design to work on digital and mixed-signal projects. Remote arrangement with relocation to onsite if converted to full-time.

You will develop RTL in VHDL, Verilog, and SystemVerilog, perform timing and verification, and collaborate with systems, firmware, and product teams. Applicants should have 7+ years, a Bachelor's in Electrical or Computer Engineering, and experience across the full design and

Qualifications

• 7+ years of ASIC and FPGA design experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Strong proficiency in VHDL, Verilog, and/or SystemVerilog.
• Experience with design verification and test bench development.
• Familiarity with Linux development environments.
• Experience across ASIC/FPGA design and implementation workflows.

Responsibilities

• Design and develop digital ASICs, FPGAs, and mixed-signal ASIC solutions.
• Develop and implement RTL using VHDL, Verilog, and/or SystemVerilog.
• Create verification methodologies, test benches, coverage models, and test plans.
• Perform timing analysis, noise analysis, and other signoff activities.
• Collaborate closely with systems, firmware, architecture, and product engineering teams.
• Support lab integration, debug, validation, and troubleshooting efforts.
• Resolve implementation challenges related to timing closure, congestion, and design optimization.

Skills

ASIC Design

FPGA Design

RTL Design

SystemVerilog

Verilog

VHDL

Design Verification

UVM

Linux

Timing Analysis

Signal Integrity

EDA Tools

Physical Design

RTL-to-GDSII

DFT

MBIST

LBIST

FinFET

CMOS

Python

TCL

Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's or PhD in Electrical Engineering, Computer Engineering, or related field

Tools

EDA Tools

RTL-to-GDSII

Python

TCL

Perl

DFT

MBIST

LBIST

Job description

Now Hiring: Sr. Design Engineer (ASIC/FPGA)

Location: Remote (Must be willing to relocate for onsite work if converted to a full-time employee)

Job Type: 6+ Month Contract (Potential Extension and/or Direct Hire Based on Performance)

We are seeking an experienced Sr. Design Engineer with a strong background in ASIC and FPGA design, verification, and implementation. This role offers the opportunity to work on cutting‑edge digital and mixed‑signal designs while collaborating with multidisciplinary engineering teams.

Key Responsibilities

• Design and develop digital ASICs, FPGAs, and mixed‑signal ASIC solutions.
• Develop and implement RTL using VHDL, Verilog, and/or SystemVerilog.
• Create verification methodologies, test benches, coverage models, and test plans.
• Perform timing analysis, noise analysis, and other signoff activities.
• Collaborate closely with systems, firmware, architecture, and product engineering teams.
• Support lab integration, debug, validation, and troubleshooting efforts.
• Resolve implementation challenges related to timing closure, congestion, and design optimization.

Required Qualifications

• 7+ years of ASIC and FPGA design experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Strong proficiency in VHDL, Verilog, and/or SystemVerilog.
• Experience with design verification and test bench development.
• Familiarity with Linux development environments.
• Experience across ASIC/FPGA design and implementation workflows.

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, or related field.
• Experience with the complete ASIC/FPGA lifecycle including architecture, design, simulation, verification, validation, integration, and testing.
• Knowledge of Software-Defined Radio (SDR), ADC/DAC, and DSP architectures.
• Understanding of communication systems, modulation techniques (QPSK, QAM, PCM/FM, PAM), spread spectrum, and forward error correction.
• Programming and scripting skills in Python, TCL, and Perl.
• Experience with industry-standard EDA tools, physical design flows, and RTL-to-GDSII implementation.
• Knowledge of FinFET and CMOS technologies.
• Experience with DFT methodologies including Scan, MBIST, and LBIST.
• Prior experience mentoring junior engineers is highly preferred.

Desired Skills

ASIC Design | FPGA Design | RTL Design | SystemVerilog | Verilog | VHDL | Design Verification | UVM | Linux | Timing Analysis | Signal Integrity | EDA Tools | Physical Design | RTL-to-GDSII | SDR | DSP | ADC/DAC | Python | TCL | Perl | DFT | MBIST | LBIST | FinFET | CMOS

Benefits Featured

• Medical, Dental , and Vision Insurance is offered to qualified candidates.