Senior Front-End Verification Engineer - RISC-V CPU

Engg; Austin, Santa Clara (TX, CA); On-site; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent, a leader in AI hardware, seeks a Design Verification Engineer to join the front-end DV team in Austin, TX or Santa Clara, CA. You will build and maintain UVM testbenches for instruction fetch units, branch predictors, and related blocks, and generate stimulus for complex microarchitectural scenarios.

The role emphasizes C++, SystemVerilog, and RTL collaboration, with opportunities across verification plans, coverage tracking, and cycle-accurate checks in a hybrid work environment.

Qualifications

• Front-end verification of CPU fetch, branch predictors, and related blocks.
• Hands-on development of unit-level DV environments and testbenches.
• Experience building reusable checkers, predictors, and transactors.
• Collaboration with RTL and software teams to trace and fix issues.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units and branch predictors.
• Develop constrained-random and directed tests targeting fetch flow and cache interactions.
• Integrate C++ reference models into the verification framework.
• Execute verification plans and track coverage, ensuring edge cases are exercised.

Skills

SystemVerilog

UVM

C++

Front-end verification

Testbenches

Constrained-random testing

BTB

TAGE predictor

RAS

Tools

Verilator

Job description

Tenstorrent, a leader in AI hardware, seeks a Design Verification Engineer to join the front-end DV team in Austin, TX or Santa Clara, CA. You will build and maintain UVM testbenches for instruction fetch units, branch predictors, and related blocks, and generate stimulus for complex microarchitectural scenarios.

The role emphasizes C++, SystemVerilog, and RTL collaboration, with opportunities across verification plans, coverage tracking, and cycle-accurate checks in a hybrid work environment.