Senior Front-End Verification Architect - RISC-V (Hybrid)

Tenstorrent; Town of Texas (WI); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end, including instruction fetch, branch prediction, and related fetch control structures. This hybrid role is based out of Austin, TX or Santa Clara, CA.

You will build testbenches with SystemVerilog and UVM, develop constrained-random stimuli, maintain C++ reference models, and work with RTL designers to debug edge cases and ensure coverage.

Qualifications

• Front-End verification of CPU front-end blocks using SystemVerilog, UVM, and C++.
• Unit-level testbench environments with precise stimulus and checking.
• Reusable design of transactors, predictors, and scoreboards.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units and branch predictors.
• Develop constrained-random and directed tests for fetch, misprediction, and cache interactions.
• Collaborate with RTL designers to trace and fix edge-case fetch bugs and ensure coverage.

Skills

Front-End Verification

Unit-Level Testing

Testbench Development

Collaboration

Tools

SystemVerilog

UVM

C++

Verilator

Job description

Tenstorrent is seeking a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end, including instruction fetch, branch prediction, and related fetch control structures. This hybrid role is based out of Austin, TX or Santa Clara, CA.

You will build testbenches with SystemVerilog and UVM, develop constrained-random stimuli, maintain C++ reference models, and work with RTL designers to debug edge cases and ensure coverage.