Hybrid Front-End Verification Engineer for RISC-V CPU

Tenstorrent; Austin (TX); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Design Verification Engineer to contribute to unit-level verification of its RISC-V CPU frontend, building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. The role is hybrid, based in Austin, TX or Santa Clara, CA, with compensation in a broad range depending on experience.

Responsibilities include building UVM testbenches for instruction fetch units, branch predictors and related blocks, developing constrained-random

Qualifications

• Unit-level verification of front-end blocks using SystemVerilog/UVM.
• Build and maintain UVM testbenches for instruction fetch and branch predictors.
• Develop constrained-random and directed tests to target misprediction and fetch flows.
• Integrate C++ reference models into verification framework.

Responsibilities

• Create testbenches and stimulus for CPU frontend with fetch, BTB, TAGE, RAS.
• Develop coverage plans and verify edge cases across pipelines.
• Collaborate with RTL, performance modeling, and software teams to ensure correctness.

Skills

SystemVerilog

UVM

C++

Testbench development

Front-end verification

Collaboration

Tools

Verilator

Job description

Tenstorrent is seeking a Design Verification Engineer to contribute to unit-level verification of its RISC-V CPU frontend, building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. The role is hybrid, based in Austin, TX or Santa Clara, CA, with compensation in a broad range depending on experience.

Responsibilities include building UVM testbenches for instruction fetch units, branch predictors and related blocks, developing constrained-random