Sr. Staff Engineer, CPU (Front-End) Verification

Engg; Austin, Santa Clara (TX, CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent, a leader in AI hardware, seeks a Design Verification Engineer to join the front-end DV team in Austin, TX or Santa Clara, CA. You will build and maintain UVM testbenches for instruction fetch units, branch predictors, and related blocks, and generate stimulus for complex microarchitectural scenarios.

The role emphasizes C++, SystemVerilog, and RTL collaboration, with opportunities across verification plans, coverage tracking, and cycle-accurate checks in a hybrid work environment.

Qualifications

• Front-end verification of CPU fetch, branch predictors, and related blocks.
• Hands-on development of unit-level DV environments and testbenches.
• Experience building reusable checkers, predictors, and transactors.
• Collaboration with RTL and software teams to trace and fix issues.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units and branch predictors.
• Develop constrained-random and directed tests targeting fetch flow and cache interactions.
• Integrate C++ reference models into the verification framework.
• Execute verification plans and track coverage, ensuring edge cases are exercised.

Skills

SystemVerilog

UVM

C++

Front-end verification

Testbenches

Constrained-random testing

BTB

TAGE predictor

RAS

Tools

Verilator

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++.
• Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking.
• Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels.
• Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs.

What We Need

• Unit-Level Verification: Work within the front-end DV team to build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.
• Stimulus Generation: Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.
• C++ Integration: Help develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking.
• Execution & Closure: Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified.

What You Will Learn

• RISC-V Front-End Microarchitecture: Practical experience with high-performance RISC-V fetch pipelines and prediction structures.
• Maintainable DV Infrastructure: Strategies for writing unit testbenches that remain manageable as designs evolve.
• Tooling & Workflows: Experience using both industry-standard simulators and open-source flows (e.g., Verilator) across simulation and emulation environments.
• Cross-Team Collaboration: Working directly with RTL, performance modeling, and software teams to deliver reliable hardware.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.