Senior Front-End Verification Engineer - RISC-V CPU

Tenstorrent; Town of Texas (WI); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Design Verification Engineer to contribute to unit-level verification of the RISC-V CPU front end, focusing on instruction fetch, branch prediction, and related fetch control structures.

Join a cross-functional DV team in a hybrid role based out of Austin, TX or Santa Clara, CA, with opportunities across software models, simulators, and open-source flows. Experience levels vary and offers align with level during the interview process.

Qualifications

• Front-end CPU blocks verification using UVM testbenches.
• Unit-level testbenches with precise stimulus and checkers.
• Reusable transactors, predictors, and scoreboards across DV levels.
• Collaborate with RTL designers to fix fetch-related bugs.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units.
• Develop constrained-random and directed tests for fetch, prediction, and cache/TLB interactions.
• Maintain and integrate C++ reference models into the verification framework.
• Execute plans, measure coverage, and drive edge-case verification closure.

Skills

Front-End Verification

Unit-Level Testing

Reusable DV Infrastructure

Collaborative Debugging

Tools

SystemVerilog

UVM

C++

Verilator

Job description

Tenstorrent is seeking a Design Verification Engineer to contribute to unit-level verification of the RISC-V CPU front end, focusing on instruction fetch, branch prediction, and related fetch control structures.

Join a cross-functional DV team in a hybrid role based out of Austin, TX or Santa Clara, CA, with opportunities across software models, simulators, and open-source flows. Experience levels vary and offers align with level during the interview process.