Senior Front-End SoC Digital Design Engineer

Lyte AI; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental, and vision coverage

401(k) retirement plan

Flexible vacation and time-off policy

Competitive salary and equity

Job summary

Lyte, Sunnyvale, CA, is seeking an experienced Front-end Digital Design Engineer to shape SoC architectures from prototype to mass production. You will define architectures, implement front-end blocks, and collaborate with backend/DFT teams to ensure robust designs and post-silicon readiness.

The role requires deep Verilog/SystemVerilog knowledge, strong synthesis experience, and excellent collaboration and communication skills.

Qualifications

• Bachelor or higher in Electrical or Computer Engineering or similar field.
• 10+ years of proven industrial experience in Digital Front-end designs.
• Proven experience in embedded and mixed-mode SoC designs.
• Deep knowledge in Verilog and SystemVerilog.
• Experience in logic synthesis.
• Strong analytical and problem-solving skills.
• Excellent written and verbal communication skills.
• Excellent teamwork capabilities.

Responsibilities

• Define the architecture and u-architecture of complex design blocks, DSP processing pipeline and SoC and document them.
• Front-end implementation of the blocks from concept to synthesis.
• Work together with the backend and DFT teams to implement the design.
• Define with the verification team the test-suite for the design, debug and fix bugs.
• Contribute to design and tool methodologies, including AI tools, in the design flow.
• Participate in silicon bringup and post-silicon debugging.

Skills

Verilog

SystemVerilog

Synthesis

Analytical skills

Communication skills

Teamwork

Education

Bachelor's or higher in Electrical/Computer Engineering

Tools

Synthesis tools

Job description

Lyte, Sunnyvale, CA, is seeking an experienced Front-end Digital Design Engineer to shape SoC architectures from prototype to mass production. You will define architectures, implement front-end blocks, and collaborate with backend/DFT teams to ensure robust designs and post-silicon readiness.

The role requires deep Verilog/SystemVerilog knowledge, strong synthesis experience, and excellent collaboration and communication skills.