Principal Front-End Design Engineer: AI-Driven SoC

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. seeks a Principal Front-End Design Engineer in Sunnyvale, CA to lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development.

You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams. The role includes developing AI-driven verification and synthesis flows, architecting reusable subsystem reference designs, and mentoring engineers.

Qualifications

• Relevant degree and extensive hands-on ASIC/SoC/IP experience.
• Proven leadership across cross-functional engineering teams.
• Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.

Responsibilities

• Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
• Architect reusable subsystem reference designs for Synopsys IP.
• Debug and optimize front-end design methodologies and automation flows.
• Drive adoption of best practices across design and verification teams.
• Collaborate with EDA, IP, and customer-facing engineers to solve design challenges.
• Mentor engineers through technical leadership and knowledge sharing.

Skills

Technical leadership

Cross-functional collaboration

Mentoring

SystemVerilog/UVM

Python

Strong problem-solving

Communication skills

Education

10+ years ASIC/SoC/IP design and verification experience

BS/MS in Electrical Engineering or Computer Engineering

Tools

VCS

VC SpyGlass

Fusion Compiler

Design Compiler

TestMAX

Job description

Synopsys, Inc. seeks a Principal Front-End Design Engineer in Sunnyvale, CA to lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development.

You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams. The role includes developing AI-driven verification and synthesis flows, architecting reusable subsystem reference designs, and mentoring engineers.