Senior FPGA Verification Lead — Equity & Impact

Anduril Industries; Goleta (CA); On-site; USD 191,000 - 253,000; Full time

Benefits offered by this job

Equity grants

Top-tier benefits

Job summary

Anduril Industries is seeking a Senior FPGA Verification Engineer on the Imaging team to define, build prototypes, and mature them into ground and flight-tested products.

The role requires a Bachelor's in Electrical/Computer Engineering and 8+ years of HDL experience with VHDL/Verilog, SystemVerilog, and UVM. Candidates should be able to lead verification efforts and collaborate across teams in a security-clearance‑eligible environment.

Qualifications

• Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• 8+ years of experience developing HDL firmware for FPGA devices
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Experience applying chip-level verification methodologies, including constrained‑random testing, functional coverage analysis, and assertion‑based verification (SystemVerilog)
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.

Responsibilities

• Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Skills

SystemVerilog / UVM

VHDL

RTL verification

Testbench development

Git / SVN

Python / scripting

Security clearance (US)

Education

Bachelor's in Electrical/Computer Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Job description

Anduril Industries is seeking a Senior FPGA Verification Engineer on the Imaging team to define, build prototypes, and mature them into ground and flight-tested products.

The role requires a Bachelor's in Electrical/Computer Engineering and 8+ years of HDL experience with VHDL/Verilog, SystemVerilog, and UVM. Candidates should be able to lead verification efforts and collaborate across teams in a security-clearance‑eligible environment.