Senior FPGA Verification Engineer — RTL, UVM Lead, Equity

Anduril Industries; Boulder (CO); On-site; USD 165,000 - 219,000; Full time

Job summary

Anduril Industries in Boulder, CO, is seeking a Senior FPGA Verification Engineer to help define and mature new product lines for defense technology. You will work with a cross‑functional team to design, develop, and verify RTL blocks using VHDL/SystemVerilog, build testbenches, and drive coverage and test plan execution through prototype to production.

The role requires 8+ years of HDL firmware experience for FPGA devices, strong verification methodologies including constrained-random testing

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8+ years of experience developing HDL firmware for FPGA devices.
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog).
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
• Eligible to obtain and maintain an active U.S. Secret security clearance

Responsibilities

• Verification environment architecture and design using SystemVerilog or OVM/UVM.
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking.
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog.
• Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA verification flow.
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Skills

HDL firmware development

RTL verification

VHDL/SystemVerilog

Constrained-random testing

Functional coverage analysis

Assertion-based verification

Git/Subversion

Unix/Linux scripting

C/C++ / Python

Technical leadership

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Job description

Anduril Industries in Boulder, CO, is seeking a Senior FPGA Verification Engineer to help define and mature new product lines for defense technology. You will work with a cross‑functional team to design, develop, and verify RTL blocks using VHDL/SystemVerilog, build testbenches, and drive coverage and test plan execution through prototype to production.

The role requires 8+ years of HDL firmware experience for FPGA devices, strong verification methodologies including constrained-random testing