Senior FPGA & SoC Design Engineer — RTL, DDR IP Lead

Lattice Semiconductor Corp; United States; On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Healthcare

Retirement plan

Paid time off

Job summary

Lattice Semiconductor Corp is seeking an experienced RTL Design Engineer in the United States to lead FPGA/SoC IP development and verification across diverse market segments. You will architect, implement and validate DDR controllers and related IPs within Lattice’s FPGA tool flows, collaborating with software and applications teams.

The role requires strong RTL, timing, and high-speed interface expertise, with leadership responsibilities and a focus on delivering high‑quality hardware designs

Qualifications

• Bachelor’s degree in Electronics Engineering, Applied Physics or related field.
• 8+ years of experience as Design Engineer or related field.
• Experience with FPGA/SoC ASIC development and IP for FPGA/ASIC products.
• FPGA RTL design, verification, debugging and timing closure.
• DDR protocols (DDR3/DDR4/LPDDR4/DDR5), high-speed interfaces.

Responsibilities

• Architect and develop DDR Memory Controller soft IPs.
• Optimize soft IPs for latency, size and frequency.
• FPGA design and implementation using software primitives.
• Integrate with third‑party hardened PHYs.
• Lead teams and manage stakeholders.
• Perform STA and constraint writing.
• Contribute to customer solution strategies.

Skills

RTL design

verification

embedded systems

team leadership

Education

Bachelor’s degree in Electronics Engineering or related field

Tools

Lattice FPGA tool flow

Static Timing Analysis (STA)

Job description

Lattice Semiconductor Corp is seeking an experienced RTL Design Engineer in the United States to lead FPGA/SoC IP development and verification across diverse market segments. You will architect, implement and validate DDR controllers and related IPs within Lattice’s FPGA tool flows, collaborating with software and applications teams.

The role requires strong RTL, timing, and high-speed interface expertise, with leadership responsibilities and a focus on delivering high‑quality hardware designs