Senior FPGA Firmware Engineer - Space Imaging

Anduril; Boulder (CO); On-site; USD 165,000 - 218,000; Full time

Benefits offered by this job

Equity compensation

Comprehensive benefits

Security clearance eligibility

Job summary

Anduril Industries seeks a Senior Firmware Engineer for the Space Imaging team to define space EO/IR payload architectures, build prototypes, and mature them into flight hardware. You will lead small teams from concept to development, collaborating across hardware and software disciplines.

Responsibilities include FPGA architecture, VHDL/Verilog design, verification with test benches, and hardware-accelerated optimization.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• 8+ years HDL firmware experience for FPGA devices.
• Expertise in VHDL and/or Verilog/SystemVerilog for RTL design.
• Experience with FPGA design tools (Vivado/Quartus).
• Strong lab debugging with standard equipment.
• Proficient with Git for collaborative development.
• U.S. Person status required and ability to obtain security clearance.

Responsibilities

• Lead FPGA architecture, standards, development and review processes.
• Design, simulate, and integrate VHDL/Verilog for FPGAs/SoCs.
• Collaborate with hardware, software and systems teams for firmware integration.
• Develop test benches and validate designs against specs and performance.
• Optimize algorithms for hardware acceleration and AXI interfaces.

Skills

HDL firmware

VHDL

Verilog/SystemVerilog

RTL design

Git version control

Debugging

US person status

Security clearance eligibility

Education

Bachelor's in Electrical/Computer Engineering

Tools

Xilinx Vivado

Intel Quartus

Oscilloscopes

Logic analyzers

Job description

Anduril Industries seeks a Senior Firmware Engineer for the Space Imaging team to define space EO/IR payload architectures, build prototypes, and mature them into flight hardware. You will lead small teams from concept to development, collaborating across hardware and software disciplines.

Responsibilities include FPGA architecture, VHDL/Verilog design, verification with test benches, and hardware-accelerated optimization.