Senior FPGA Digital Design Engineer (Level 5) - Secret Clearance

Northrop Grumman; United States; Vor Ort; USD 195.000 - 292.000; Vollzeit

Benefits dieser Stelle

Relocation assistance may be available

Health insurance

Life and disability insurance

Savings plan

Paid time off

Zusammenfassung

Northrop Grumman is seeking a Staff FPGA Digital Design Engineer (Level 5) to support the ARRGM-ER missile program in Northridge, CA. The role will focus on FPGA/ASIC design across the full product life cycle, using Model-based Engineering, DevSecOps and Agile practices.

This on-site position requires a Secret clearance and offers competitive base salary with potential bonuses and a full benefits package.

Qualifikationen

• Bachelor's degree in electrical engineering or STEM with 12 years of digital design & verification experience, or 10 years with MS.
• Hands-on FPGA design experience with VHDL and/or Verilog in the past 6 years.
• Experience with AMD/Xilinx and/or Intel/Altera SoC FPGAs.
• Experience with EDA tools: Vivado, Quartus, QuestaSim.
• Must be able to obtain an Active US Government Secret security clearance.

Aufgaben

• Design, develop, modify and evaluate digital circuitry for digital electronic equipment.
• Determine design approaches and parameters.
• Analyze equipment to establish operating data and conduct tests.
• Select components based on specs and reliability.
• Review vendor capability to support product development.
• Research, design and develop for complex high-speed digital designs
• Support implementation of digital FPGA hardware architecture and algorithms
• Collaborate with Systems Engineering to ensure firmware meets system requirements
• Review designs and analyses

Kenntnisse

FPGA design

VHDL

Verilog

Xilinx/AMD SoC FPGA

Intel/Altera SoC FPGA

EDA tools (Vivado/Quartus/QuestaSim)

DSP concepts

RF design (plus)

Model-based Engineering/DevSecOps/Agle

Ausbildung

Bachelor's degree in electrical engineering or STEM

Tools

Vivado

Quartus

QuestaSim

Modelsim

Jobbeschreibung

Northrop Grumman is seeking a Staff FPGA Digital Design Engineer (Level 5) to support the ARRGM-ER missile program in Northridge, CA. The role will focus on FPGA/ASIC design across the full product life cycle, using Model-based Engineering, DevSecOps and Agile practices.

This on-site position requires a Secret clearance and offers competitive base salary with potential bonuses and a full benefits package.