Senior FPGA Digital Engineer (Secret Clearance)

Northrop Grumman Corp.; Chandler (AZ); Sur place; USD 108 000 - 162 000; Plein temps

Avantages offerts par ce poste

Relocation assistance

Secret clearance

Travel opportunities

Résumé du poste

Northrop Grumman Space Systems in Chandler, AZ is seeking a Staff FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will apply advanced FPGA engineering principles, lead design challenges, and develop high-level test benches for timing-critical FPGA designs.

The role requires mastery of VHDL/Verilog, extensive Xilinx FPGA/SoC experience, and verification with OSVVM/UVM and Questa/ModelSim. Travel up to 10% may be required and DoD Secret clearance is required.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university.
• Advanced background in FPGA/SoC design with mastery in complex firmware development using VHDL (preferred) or Verilog.
• Extensive experience with AMD Xilinx FPGAs and SoCs, managing design constraints (timing, power, I/O) and performing static timing analysis.

Responsabilités

• Lead resolution of design and integration challenges across hardware, algorithms, and software teams.
• Develop and execute high-level test benches to verify FPGA designs for timing and functional correctness.
• Generate, verify, and integrate HDL modules and interfaces (Ethernet, PCIe, AXI4, UART, SDLC).
• Prepare, present, and maintain design documentation and verification reports.
• Stay abreast of evolving FPGA technologies and tools.

Connaissances

FPGA design

VHDL/Verilog

Xilinx FPGAs/SoCs

OSVVM/UVM verification

Questa/ModelSim

Timing analysis

DDR memory interfaces

Formation

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline

MS or PhD in Electrical Engineering, Computer Engineering, or related discipline

Outils

Vivado IDE

Vitis Unified IDE

OSVVM

OSVVM/UVM tooling

Questa/ModelSim

Logic analyzers

Oscilloscopes

Description du poste

Northrop Grumman Space Systems in Chandler, AZ is seeking a Staff FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will apply advanced FPGA engineering principles, lead design challenges, and develop high-level test benches for timing-critical FPGA designs.

The role requires mastery of VHDL/Verilog, extensive Xilinx FPGA/SoC experience, and verification with OSVVM/UVM and Questa/ModelSim. Travel up to 10% may be required and DoD Secret clearance is required.