Senior FPGA Design Lead

Jabil; Austin (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

Jabil is seeking an FPGA Lead Engineer to drive design, development, integration, and debugging for server, storage, networking, and AI infrastructure platforms. You will own FPGA architecture, RTL, verification readiness, hardware bring-up, and cross‑functional issue resolution.

The role requires leadership of design reviews, risk assessment, and collaboration with multiple engineering teams to ensure schedule, manufacturability, and customer quality targets are met.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• Master’s degree preferred.
• 5–10 years of FPGA design and hardware integration experience.

Responsibilities

• Lead FPGA design, development, integration, and debug for server/storage/networking/AI platforms.
• Own FPGA architecture, RTL implementation, verification readiness, and bring-up.
• Mentor engineers and drive design reviews, requirements traceability, and issue resolution.
• Collaborate with Electrical, BIOS, BMC, Systems, Validation, Manufacturing, and customer teams to resolve cross-domain issues.

Skills

FPGA design

RTL development

Simulation

Synthesis

Timing analysis

Lab-based debugging

FPGA toolchains (AMD/Xilinx, Intel/Al­

Digital interfaces (SPI, I2C, UART, -E

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Master’s degree preferred

Tools

AMD/Xilinx toolchains

Intel/Altera tools

Job description

Jabil is seeking an FPGA Lead Engineer to drive design, development, integration, and debugging for server, storage, networking, and AI infrastructure platforms. You will own FPGA architecture, RTL, verification readiness, hardware bring-up, and cross‑functional issue resolution.

The role requires leadership of design reviews, risk assessment, and collaboration with multiple engineering teams to ensure schedule, manufacturability, and customer quality targets are met.