FPGA Implementation Engineer 5

Cts Technology Solutions, Inc.; El Segundo (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

CTS (the contractor) will lead FPGA/ASIC design projects in a 100% onsite setting in the United States, focusing on Verilog/SystemVerilog and Versal-based devices. The role requires a Secret clearance to start and involves updating constraints, synthesis, simulation, and Place & Route to ensure timing closure and design integrity.

The candidate will program FPGA devices primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families, and collaborate with system engineering for

Qualifications

• 5+ years FPGA/ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Secret Clearance required.

Responsibilities

• Inherit FPGA top-level design and add new blocks and interfaces, integrate third-party and in-house IP cores.
• Update constraint files, perform synthesis, simulation, and Place & Route for timing closure and design integrity.
• Program FPGA devices, primarily Versal, Ultrascale, and Ultrascale+ families.
• Collaborate with system engineering to support hardware and software integration and testing.
• Produce high-quality technical documentation and deliver maintainable engineering solutions.
• On-site work required.

Skills

5+ years FPGA/ASIC design

Xilinx/AMD Vivado

Versal family devices

Verilog/SystemVerilog

FPGA implementation (synthesis, timing

Secret Clearance

Education

Bachelor's degree in engineering/related field

Advanced degree (MS/PhD) preferred

Tools

Xilinx Vivado

Job description

Takes about 3 minutes. No account required.

Position

Overview

**Secret Clearance Required to Start.**

100% onsite.

The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.

Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.

Across all positions, we are looking for engineers who:
Demonstrate strong digital hardware fundamentals.
Exercise sound engineering judgment.
Work independently with minimal oversight.
Communicate clearly and proactively.
Produce high-quality technical documentation.
Take ownership of their work and deliver maintainable engineering solutions.

6+ months — possible extension and possible FTE opportunity.

Requirements

What you\'ll need

Required Skills:
5+ years of FPGA and/or ASIC design experience;
strong Xilinx/AMD Vivado experience;
Experience with Versal family devices;
Verilog/SystemVerilog HDL proficiency required;
Advanced FPGA implementation skills (synthesis, timing closure, constraints);
Secret Clearance

Preferred Skills:
2+ years of FPGA design experience;
strong Xilinx/AMD Vivado experience;
Verilog/SystemVerilog proficiency;
Advanced FPGA implementation skills (synthesis, timing closure, constraints);

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years\' related work experience (e.g. PhD+9 years\' related work experience, Master+12 years\' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

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