Senior FPGA Design Engineer - Versal/Ultrascale (Contract)

A2e-Technologies; San Diego (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

A2e Technologies seeks a Sr. FPGA Design Engineer in Redmond for a long-term contract with potential for permanency and an ASAP start.

The role centers on FPGA/modem design using Ultrascale+ and Versal, requiring VHDL and SystemVerilog, plus design and simulation and high-speed SerDes development. Candidates should have 10+ years of experience, strong scripting (Python, Perl, Bash, TCL), and hands-on work with Ethernet, PCIe, SPI, I2C, and UART interfaces.

Qualifications

• 10+ years of FPGA/Modem design experience.
• Experience with Ultrascale and Versal architectures.
• Proficiency in VHDL and SystemVerilog.
• Experience in high-speed SerDes and design/simulation.
• Strong scripting skills including Python, Perl, Bash, and Tcl.

Skills

FPGA/Modem Design

Ultrascale+ & Versal

VHDL & SystemVerilog

High-speed Serdes

Design and Simulation

Scripting (Python, Perl, Bash, TCL)

Ethernet PCIe SPI I2C UART

10+ Years Experience

Tools

Petalinux

Job description

A2e Technologies seeks a Sr. FPGA Design Engineer in Redmond for a long-term contract with potential for permanency and an ASAP start.

The role centers on FPGA/modem design using Ultrascale+ and Versal, requiring VHDL and SystemVerilog, plus design and simulation and high-speed SerDes development. Candidates should have 10+ years of experience, strong scripting (Python, Perl, Bash, TCL), and hands-on work with Ethernet, PCIe, SPI, I2C, and UART interfaces.