Electrical Design and Analyst Engineer 5

CHIPTON-ROSS Inc.; El Segundo (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Chipton-Ross Inc. seeks an Electrical Design and Analyst Engineer for a contract in El Segundo, CA. The role is 100% onsite, non-managerial, focused on FPGA/ASIC design, verification, and integration.

Ideal candidates have 5+ years of FPGA experience, Proficiency in Verilog/SystemVerilog, and hands-on work with Xilinx Vivado and Versal devices. Strong documentation and independent work are essential.

Qualifications

• Bachelor's degree in engineering, computer science or related field.
• 5+ years FPGA/ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency.
• Advanced FPGA implementation: synthesis, timing closure, constraints.

Responsibilities

• Inherit FPGA top-level design and add new functional blocks.
• Integrate third-party and in-house IP cores.
• Update constraint files, perform synthesis, simulation, Place & Route for timing.
• Program FPGA devices, primarily Versal/Ultrascale families.
• Collaborate with system engineering for hardware/software integration; on-site work.

Skills

FPGA/ASIC design

Verilog/SystemVerilog

Xilinx Vivado

Versal devices

Timing closure

Education

Bachelor of Science in engineering/computer science

Job description

Chipton-Ross is seeking 10 Electrical Design and Analyst Engineer 5 for a contract opportunity in El Segundo, CA.

100% onsite

BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE):

• Regular and predictable attendance is required.
• 5+ years of FPGA and/or ASIC design experience.
• strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency required.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).

Across all positions, we are looking for engineers who:

• Demonstrate strong digital hardware fundamentals.
• Exercise sound engineering judgment.
• Work independently with minimal oversight.
• Communicate clearly and proactively.
• Produce high-quality technical documentation.
• Take ownership of their work and deliver maintainable engineering solutions.
• Recruiters should prioritize candidates who can clearly explain their personal technical contributions, design decisions, debugging approach, and ownership of deliverables, rather than simply listing tools or technologies used on a project.

POSITION RESPONSIBILITIES:

The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.

Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.

Work statement is a non-managerial role, non-leadership role.

PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE):

• 2+ years of FPGA design experience.
• strong Xilinx/AMD Vivado experience.
• Verilog/SystemVerilog proficiency.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).

REQUIRED EDUCATION:

Minimum of a Bachelor of Science degree from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

WORK HOURS:

• Full-Time/First Shift
• 8:00 AM - 4:30 PM
• Possible OT opportunities.

ADDITIONAL:

Applicants responding to this position will be subject to a government security investigation and must meet eligibility requirements by currently possessing the ability to view classified government information.