Senior FPGA Design Engineer - Versal/Ultrascale, Serdes

A2e Technologies; Los Angeles (CA); On-site; USD 165,000 - 248,000; Full time

Job summary

A2e Technologies is seeking a Sr. FPGA Design Engineer in Redmond for a long-term contract (possible permanent) engagement starting ASAP.

The role requires 10+ years of FPGA/Modem Design experience with Ultrascale+ and Versal, and strong VHDL/SystemVerilog skills. Responsibilities include design and simulation of high-speed SERDES and implementation of robust communication interfaces such as Ethernet, PCIe, SPI, I2C, and UART.

Qualifications

• 10+ years experience in FPGA/Modem Design.
• Experience with Ultrascale+ and Versal.
• Proficiency in VHDL and SystemVerilog.
• Design and simulate high-speed interfaces.
• Strong scripting skills (Python, Tcl, Bash).

Responsibilities

• Solid communication interfaces such as Ethernet, Interlocken, PCIe, SPI, I2C, UART, etc.

Skills

FPGA Design

Modem Design

Ultrascale/Versal

VHDL

SystemVerilog

Design & Simulation

High-speed SerDes

Scripting (Python etc)

Job description

A2e Technologies is seeking a Sr. FPGA Design Engineer in Redmond for a long-term contract (possible permanent) engagement starting ASAP.

The role requires 10+ years of FPGA/Modem Design experience with Ultrascale+ and Versal, and strong VHDL/SystemVerilog skills. Responsibilities include design and simulation of high-speed SERDES and implementation of robust communication interfaces such as Ethernet, PCIe, SPI, I2C, and UART.