FPGA Design Engineer – Versal, HDL & Timing

CTS International; El Segundo (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

CTS International seeks a contractor to analyze requirements and develop architectural approaches and detailed FPGA specifications for advanced electronic products. You will inherit top-level FPGA design responsibilities, add new functional blocks, integrate IP cores, update constraints, perform synthesis, simulation, and Place & Route to ensure timing closure and design integrity.

You will collaborate with system engineering to support hardware/software integration, testing activities, and

Qualifications

• 2+ years of FPGA design experience.
• 5+ years of FPGA/ASIC design experience preferred.
• Experience with Versal family devices preferred.

Responsibilities

• Analyze customer and system requirements to develop architectural and detailed specifications.
• Create FPGA top-level and block-level designs, including integrating third-party and in-house IP cores.
• Perform synthesis, simulation, placement & routing to ensure timing closure and design integrity.
• Troubleshoot timing violations and produce HDL designs beyond IP instantiation.
• Collaborate with system engineering for hardware/software integration and testing.

Skills

FPGA design

HDL (Verilog/VHDL)

Synthesis

Timing closure

Constraints

Versal devices

Xilinx FPGA

Digital design

Education

Bachelor's degree in engineering/CS/math/physics/chemistry

ABET accreditation (USA)

Tools

Xilinx Vivado

ModelSim/Simulators

Job description

CTS International seeks a contractor to analyze requirements and develop architectural approaches and detailed FPGA specifications for advanced electronic products. You will inherit top-level FPGA design responsibilities, add new functional blocks, integrate IP cores, update constraints, perform synthesis, simulation, and Place & Route to ensure timing closure and design integrity.

You will collaborate with system engineering to support hardware/software integration, testing activities, and