Senior FPGA Design Engineer — Onsite, Clearance-Ready

RTX; Miami (FL); On-site; USD 86,000 - 165,000; Full time

Benefits offered by this job

Relocation Assistance

9/8 Schedule – every other Friday off

Job summary

RTX is seeking a Senior FPGA Design Engineer in Tucson, AZ to develop FPGA designs for Xilinx, Altera, and Microsemi families. You will work with VHDL to implement gigabit serial interfaces, RF/EO DSP, controls and data links, collaborating with circuit card designers and systems engineers.

You will translate requirements into FPGA designs, verify with directed and constrained random tests, document requirements and verification plans, and mentor junior engineers while supporting reviews and

Qualifications

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM).
• Minimum of 5 years of prior relevant experience in FPGA design.

Responsibilities

• Design and deliver production quality FPGA releases from initial proof of concept up to production.
• Architect FPGA-based systems to determine parts, interfaces, and CONOPS.
• Translate system level requirements into FPGA requirements.
• Design and code in VHDL for reliability and maintainability.
• Verify designs with directed and constrained random tests and track coverage.
• Support project schedules on time and budget.
• Create documentation including requirements, verification plan, and user guides.
• Lead small teams and mentor junior engineers.
• Support internal and external technical reviews.

Skills

VHDL

Verilog

SystemVerilog

Xilinx devices

Microsemi devices

FPGA design

Education

STEM degree

Tools

Xilinx tools

Microsemi tools

Job description

RTX is seeking a Senior FPGA Design Engineer in Tucson, AZ to develop FPGA designs for Xilinx, Altera, and Microsemi families. You will work with VHDL to implement gigabit serial interfaces, RF/EO DSP, controls and data links, collaborating with circuit card designers and systems engineers.

You will translate requirements into FPGA designs, verify with directed and constrained random tests, document requirements and verification plans, and mentor junior engineers while supporting reviews and