Senior FPGA Architect for DoD Systems | Onsite Tucson

RTX

Phoenix (AZ)

On-site

USD 108,000 - 205,000

Full time

14 days+

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Benefits offered by this job

Relocation offered

Job summary

RTX in Tucson, AZ is seeking a Principal FPGA Design Engineer to develop FPGA designs for major vendors and device families. Expertise in VHDL/Verilog and FPGA/ASIC delivery is required, with hands-on debugging and integration across teams.

The role is 100% onsite in Tucson, with a DoD Secret clearance requirement and relocation support. Candidates should have 8+ years of FPGA/ASIC experience and knowledge of Xilinx or Microsemi tools.

Qualifications

  • Degree in Science, Technology, Engineering or Mathematics (STEM) with 8+ years of relevant FPGA/ASIC experience.
  • FPGA/ASIC design or verification experience with HDL coding (VHDL/Verilog/SystemVerilog).
  • Experience with Xilinx or Microsemi devices and flow tools.
  • Experience delivering FPGA/ASIC solutions to system-level applications.
  • Hands-on integration, debugging and verification across teams.

Responsibilities

  • Deliver production-quality FPGA releases from proof of concept to production.
  • Architect FPGA-based systems and determine parts, interfaces, and CONOPS.
  • Translate system requirements into FPGA requirements and code in VHDL/Verilog.
  • Verify designs using directed tests and constrained random methods; ensure coverage.
  • Lead projects, manage schedules, and create design documentation.

Skills

FPGA/ASIC design
VHDL
Verilog
SystemVerilog
C-level HDL

Education

STEM degree

Tools

Xilinx devices
Microsemi devices
Device flow tools

Job description

RTX in Tucson, AZ is seeking a Principal FPGA Design Engineer to develop FPGA designs for major vendors and device families. Expertise in VHDL/Verilog and FPGA/ASIC delivery is required, with hands-on debugging and integration across teams.

The role is 100% onsite in Tucson, with a DoD Secret clearance requirement and relocation support. Candidates should have 8+ years of FPGA/ASIC experience and knowledge of Xilinx or Microsemi tools.

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