Senior Formal Verification Engineer – Chip Interconnect

Advanced Micro Devices; Austin (TX); Hybrid; USD 140,000 - 190,000; Full time

Job summary

AMD in Austin, TX is seeking a senior verification engineer to lead formal verification efforts for configurable switches and die-to-die interconnects. You will apply VC Formal and JasperGold to prove properties, discover corner-case bugs, and work closely with RTL designers to shift verification left.

The role requires 8+ years in design verification with a focus on formal methods, strong SVA knowledge, mentoring of engineers, and the ability to define verification plans that integrate formal

Qualifications

• Hands-on experience with VC Formal (Synopsys) and/or JasperGold (Cadence).
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification.
• Experience with FPV, connectivity checking, register verification, and equivalence checking.
• Familiarity with scripting languages (TCL, Python, Perl) for flow automation.

Responsibilities

• Develop and execute formal verification strategies using VC Formal and JasperGold.
• Write, review, and debug SystemVerilog Assertions to verify complex design behaviors.
• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning.
• Collaborate with RTL designers and architects to define verification plans that incorporate formal methods alongside simulation-based approaches.
• Identify and pursue opportunities to apply formal verification to new design blocks, championing a "formal-first" or "shift-left" verification strategy.
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows.
• Mentor and guide MTS and junior engineers in formal verification techniques and best practices.

Skills

Formal verification

SystemVerilog Assertions (SVA)

Verification planning & mentoring

Scripting (TCL, Python, Perl)

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

VC Formal (Synopsys)

JasperGold (Cadence)

Job description

AMD in Austin, TX is seeking a senior verification engineer to lead formal verification efforts for configurable switches and die-to-die interconnects. You will apply VC Formal and JasperGold to prove properties, discover corner-case bugs, and work closely with RTL designers to shift verification left.

The role requires 8+ years in design verification with a focus on formal methods, strong SVA knowledge, mentoring of engineers, and the ability to define verification plans that integrate formal