Senior Formal Verification Engineer - Interconnects

NVIDIA; Austin (TX); On-site; USD 168,000 - 264,500; Full time

Benefits offered by this job

Equity

Comprehensive benefits package

Job summary

A leading technology company in Austin, Texas is seeking a Formal Verification Engineer to verify cutting-edge chip designs. Responsibilities include developing verification methodologies and collaborating with skilled engineers to ensure design correctness. Applicants should have at least 7 years of experience in relevant fields, a strong understanding of architectures, and hands-on HDL experience. The position offers a competitive salary range of $168,000 – $264,500 for Level 4, and $196,000 – $310,500 for Level 5, along with equity and benefits.

Qualifications

• 7+ years of experience in a relevant field.
• Hands-on experience with complex RTL.
• Ability to implement effective abstraction techniques.

Responsibilities

• Identify key behaviors for verification and write test plans.
• Implement formal techniques for verification.
• Develop models to handle complexity and obtain proofs.
• Collaborate with architects, designers, and verification teams.

Skills

Solid understanding of GPU/CPU architectures

Analytical skills

Knowledge of formal verification methodologies

Experience with Verilog/SystemVerilog HDLs

Scripting using TCL, Perl, and Python

Education

BS, MS, or PhD in CS/CE/EE/Mathematics

Tools

Jasper Gold

VC Formal

Job description

A leading technology company in Austin, Texas is seeking a Formal Verification Engineer to verify cutting-edge chip designs. Responsibilities include developing verification methodologies and collaborating with skilled engineers to ensure design correctness. Applicants should have at least 7 years of experience in relevant fields, a strong understanding of architectures, and hands-on HDL experience. The position offers a competitive salary range of $168,000 – $264,500 for Level 4, and $196,000 – $310,500 for Level 5, along with equity and benefits.