Formal Verification Engineer

Advanced Micro Devices; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

AMD in Austin, TX is seeking a senior verification engineer to lead formal verification efforts for configurable switches and die-to-die interconnects. You will apply VC Formal and JasperGold to prove properties, discover corner-case bugs, and work closely with RTL designers to shift verification left.

The role requires 8+ years in design verification with a focus on formal methods, strong SVA knowledge, mentoring of engineers, and the ability to define verification plans that integrate formal

Qualifications

• Hands-on experience with VC Formal (Synopsys) and/or JasperGold (Cadence).
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification.
• Experience with FPV, connectivity checking, register verification, and equivalence checking.
• Familiarity with scripting languages (TCL, Python, Perl) for flow automation.

Responsibilities

• Develop and execute formal verification strategies using VC Formal and JasperGold.
• Write, review, and debug SystemVerilog Assertions to verify complex design behaviors.
• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning.
• Collaborate with RTL designers and architects to define verification plans that incorporate formal methods alongside simulation-based approaches.
• Identify and pursue opportunities to apply formal verification to new design blocks, championing a "formal-first" or "shift-left" verification strategy.
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows.
• Mentor and guide MTS and junior engineers in formal verification techniques and best practices.

Skills

Formal verification

SystemVerilog Assertions (SVA)

Verification planning & mentoring

Scripting (TCL, Python, Perl)

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

VC Formal (Synopsys)

JasperGold (Cadence)

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

The Infinity Fabric network on the chip verification team is growing and looking for qualified candidates to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed for AI/ML, Client, Server, Graphic Accelerator, and Semi-Custom markets.

THE PERSON:

Team is seeking a highly skilled and motivated person to join our verification team. In this role, you will drive formal verification efforts across complex hardware designs, applying rigorous mathematical methods to prove design correctness and find corner-case bugs that escape simulation. You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to shift verification left and improve overall design quality.

KEY RESPONSIBLITIES:

• Develop and execute formal verification strategies using VC Formal and/or JasperGold for property checking (FPV), connectivity checking (CC), register verification (FRV), and sequential equivalence checking (SEQ)

• Write, review, and debug SystemVerilog Assertions (SVA) — including assumptions, assertions, and cover properties — to verify complex design behaviors

• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning

• Collaborate with RTL designers and architects to define verification plans that incorporate formal methods alongside simulation-based approaches

• Identify and pursue opportunities to apply formal verification to new design blocks, championing a "formal-first" or "shift-left" verification strategy

• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows

• Mentor and guide MTS and junior engineers in formal verification techniques and best practices

REFERRED EXPERIENCE:

• Hands-on experience with VC Formal (Synopsys) and/or JasperGold (Cadence)

• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification

• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis

• Familiarity with scripting languages (TCL, Python, Perl) for flow automation

• Minimum 8+ years of experience in design verification with a strong focus on formal verification

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:

Austin, TX; Boston, MA and Santa Clara, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.