Lead ASIC Formal Verification Architect

AMD; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

AMD is seeking an experienced ASIC Formal Verification Architect to join the IOHUB team. You will lead a team of formal verification engineers, define architectures and methodologies, and drive verification closure across SoC projects.

Strong leadership, deep formal methods, and collaboration with design teams are essential. Ideal candidates will have BS/MS in engineering or CS and expertise in JasperGold/VC-formal, with UVM bridging between formal and simulation flows.

Qualifications

• BS/MS in Electrical/Electrical/Computer Engineering or Computer Science.
• Strong expertise in formal verification methodologies (Static/Dynamic) and verification closure.
• Proven leadership experience guiding technical teams and mentoring engineers.

Responsibilities

• Lead and mentor a team of formal verification engineers across multiple IP and SoC projects.
• Define and drive formal verification architecture, methodologies, and development plans with IP architects and design teams.
• Develop formal verification test plans and execute verification closure strategies.
• Architect and maintain reusable formal verification environments and components.
• Drive adoption of best practices across the organization.

Skills

Formal verification

Leadership

Communication

Problem solving

Team mentoring

Education

BS/MS in Engineering or Computer Science

Tools

JasperGold

VC-formal

UVM

Job description

AMD is seeking an experienced ASIC Formal Verification Architect to join the IOHUB team. You will lead a team of formal verification engineers, define architectures and methodologies, and drive verification closure across SoC projects.

Strong leadership, deep formal methods, and collaboration with design teams are essential. Ideal candidates will have BS/MS in engineering or CS and expertise in JasperGold/VC-formal, with UVM bridging between formal and simulation flows.