IP Verification Engineer – PCIe/CXL ASICs & UVM

AMD; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose/San Diego/Austin/Longmont is seeking an IP verification engineer to verify complex PCIe and CXL IPs across front-end design/integration teams. You will work with architecture, IP design, PD, and product engineers to achieve first pass silicon success.

You should excel in Verilog/SystemVerilog, UVM-based verification, and scripting, with strong communication and cross-site collaboration. End-to-end verification across features and drivers is expected.

Qualifications

• Experience with PCIe/CXL/NVMe or Ethernet protocols.
• AIP-level ASIC verification proficiency.
• Expert in Verilog and SystemVerilog; OO programming.

Responsibilities

• Collaborate with architects, hardware and firmware engineers to verify new PCIe CXL based IP features.
• Develop test plan documentation considering hardware/firmware/software interactions.
• Code IP or SS level UVM based testbenches, monitors, scoreboard and checkers.
• Build directed and random verification tests.
• Run regressions and debug failures to ensure design quality.

Skills

Verilog

SystemVerilog

UVM

Python

C/C++

Object Oriented programming

Debugging

Communication

Education

Bachelor's or Master's degree in computer engineering/Electrical Engineering

Tools

UVM framework

PCIe verification tools

CXL

NVMe

Job description

AMD in San Jose/San Diego/Austin/Longmont is seeking an IP verification engineer to verify complex PCIe and CXL IPs across front-end design/integration teams. You will work with architecture, IP design, PD, and product engineers to achieve first pass silicon success.

You should excel in Verilog/SystemVerilog, UVM-based verification, and scripting, with strong communication and cross-site collaboration. End-to-end verification across features and drivers is expected.