Senior Formal Verification Engineer — AI/ML SoC

AMD; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD in Austin, TX is seeking an expert in formal verification to drive verification strategies for complex hardware designs. You will work with RTL teams and architects, using advanced formal methods to prove correctness and catch corner-case bugs beyond simulation.

Strong mentoring skills and hands-on verification with SystemVerilog Assertions are essential. The role emphasizes shifting verification left, building reusable formal infrastructure, and collaborating across chip teams to improve

Qualifications

• 8+ years of design verification experience with a focus on formal verification
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
• Experience mentoring junior engineers and collaborating with RTL designers and architects

Responsibilities

• Develop and execute formal verification strategies using VC Formal and/or JasperGold for property checking (FPV), connectivity checking (CC), register verification (FRV), and sequential equivalence checking (SEQ)
• Write, review, and debug SystemVerilog Assertions (SVA) including assumptions, assertions, and cover properties
• Drive convergence on formal proofs by applying abstraction techniques and assume-guarantee reasoning
• Collaborate with RTL designers and architects to define verification plans with formal methods alongside simulation
• Identify opportunities to apply formal verification to new design blocks and promote a formal-first/shift-left approach
• Develop reusable formal verification infrastructure and automated regression flows
• Mentor and guide engineers in formal verification techniques and best practices

Skills

Formal verification

SVA

FPV

RC/CC/SEQ knowledge

Scripting (TCL/Python/Perl)

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

VC Formal (Synopsys)

JasperGold (Cadence)

Job description

AMD in Austin, TX is seeking an expert in formal verification to drive verification strategies for complex hardware designs. You will work with RTL teams and architects, using advanced formal methods to prove correctness and catch corner-case bugs beyond simulation.

Strong mentoring skills and hands-on verification with SystemVerilog Assertions are essential. The role emphasizes shifting verification left, building reusable formal infrastructure, and collaborating across chip teams to improve