Principal Firmware Engineer

Cadence Design Systems; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Cadence Design Systems in Austin is seeking a firmware engineer to join the DDR5 PHY IP Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers and C, creating bare-metal APIs and collaborating with hardware designers and memory subsystem architects.

You will also work with verification teams on firmware-hardware co-verification, debug RTL-based simulations, and assist on silicon bring-up boards, contributing to high-speed interfaces and tooling with scripting.

Qualifications

• Experience in bare-metal firmware for high-speed SerDes or memory interface PHY blocks.
• Knowledge of C for embedded software and IDE usage.
• Good knowledge of DDR5 JEDEC and DIMM configurations/specifications.
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystems.

Responsibilities

• Develop firmware for DDR5 PHY using microcontrollers.
• Develop firmware in C with bare-metal APIs on MCUs.
• Collaborate with hardware designers to derive training algorithms and implement them.
• Collaborate with verification team for firmware-hardware co-verification planning.
• Develop and debug firmware in RTL-based hardware simulations (C + Verilog).
• Develop and debug on silicon bring-up boards.

Skills

DDR5 knowledge

Bare-metal firmware

C programming

Scripting TCL/Python

RTL debugging

Silicon bring-up

Tools

Verilog

EDA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Be part of the Cadence DDR PHY IP Front End Design team responsible for

• Develop firmware for DDR5 PHY using microcontrollers
• Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.
• Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.
• Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.
• Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)
• Develop and Debug on Silicon bring-up boards.

Required Skills:

• Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.
• Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.
• Good Knowledge of C programming language for embedded software development and use of relevant IDE.
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
• Good knowledge of Shell/Perl/Python/TCL scripting
• Good experience on Verification EDA Tools like simulators and waveform viewers

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.