DRAM PHY Design Engineer

Etron Technology Inc. 鈺創科技; San Antonio (TX); On-site; USD 90,000 - 180,000; Full time

Job summary

Etron Technology Inc. 鈺創科技 is seeking an experienced DRAM PHY design engineer to lead high-speed interface development and signal integrity across global projects.

You will design and verify DRAM PHY circuits, contribute to architecture, calibrate timing, and collaborate with international teams in the U.S., Taiwan, and Japan to ensure robust silicon bring-up and performance while meeting stringent power and area targets.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or a related field.
• Experience in DRAM PHY or high-speed interface circuit design.
• Knowledge of DRAM interfaces, signal integrity, timing calibration, and impedance matching.
• Strong problem-solving, communication, and teamwork skills.

Responsibilities

• Design and develop DRAM PHY circuits supporting high-speed bidirectional data transmission.
• Contribute to PHY architecture definition and implementation based on product requirements.
• Signal integrity and interface optimization.
• Analyze and optimize signal integrity and impedance matching.
• Calibration and PHY Training.
• Develop timing and latency calibration mechanisms.
• Design and verify PHY training mechanisms to ensure reliable data transmission.
• Verification and Cross-Team Collaboration.
• Collaborate with design, verification, and system teams to validate PHY functionality and performance.
• Support issue analysis, debugging, and silicon bring-up.
• Work closely with engineering teams in the U.S., Taiwan, and Japan.

Skills

Signal integrity

Interface optimization

PHY training

Cross-team collaboration

Problem-solving

Communication

Teamwork

Education

Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related field

Job description

• Design and develop DRAM PHY circuits supporting high-speed bidirectional data transmission.
• Contribute to PHY architecture definition and implementation based on product requirements.
• Signal Integrity and Interface Optimization
• Analyze and optimize signal integrity and impedance matching.
• Develop voltage level translation circuits to meet interface requirements.
• Calibration and PHY Training
• Develop timing and latency calibration mechanisms.
• Design and verify PHY training mechanisms to ensure reliable data transmission.
• Verification and Cross-Team Collaboration
• Collaborate with design, verification, and system teams to validate PHY functionality and performance.
• Support issue analysis, debugging, and silicon bring-up.
• Work closely with engineering teams in the U.S., Taiwan, and Japan.

Required Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or a related field.
• Experience in DRAM PHY or high-speed interface circuit design.
• Knowledge of DRAM interfaces, signal integrity, timing calibration, and impedance matching.
• Strong problem-solving, communication, and teamwork skills.

Preferred Qualifications

• Experience with DDR5 or LPDDR PHY design.