Senior EMIR Engineer: Power Integrity for AI SoCs

Amazon Inc.; Cupertino, Austin (CA, TX); On-site; USD 213,000 - 288,000; Full time

Benefits offered by this job

Health insurance

RSUs

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Job summary

Amazon is seeking a Sr. EMIR Engineer to join the MLA team in Cupertino, CA. You will define EMIR sign‑off for Inf/Trainium SoCs, model demand currents, and collaborate with architects, designers and power/thermal experts to ensure robust IR and power integrity across die, package and board levels.

You will design and run EMIR analyses, develop vectors, dashboards, and best practices, and partner with EDA vendors to advance methodologies. A strong background in ASIC power integrity is essential.

Qualifications

• 5+ years of ASIC implementation, synthesis, STA and physical design in deep sub‑micron nodes (16nm or smaller) experience.
• BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS.
• Expert on EMIR analysis tools like Redhawk‑SC or Voltus or similar.
• Deep, circuit‑level understanding of power, EM and IR.
• Ability to give feedback to RTL designers and Physical Designers on how to reduce IR.
• Highly proficient with scripting language (Tcl, Perl, Python or similar).
• Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level.

Responsibilities

• Design & analyze power grids.
• Setup flows for EMIR analysis.
• Run EMIR analysis for large subsystems, SoCs.
• Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis.
• Develop and maintain dashboards for EMIR rollups.
• Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation.
• Design and evaluate power grids.
• Working with designers, architects and verification engineers to come up with worst‑case vectors for power and IR analysis.
• Root cause causes of low annotation or low switching coverage with vectors.
• Develop & maintain dashboards to track EMIR status.
• Root cause causes of IR drop and suggest solutions to fix.
• Combine IR analysis of SoC with IR at board and package level (concurrent IR analysis).
• Do post-silicon power measurements and correlate with simulation.
• Innovate on ways to model VR, board and package impact on voltage drop more accurately.
• Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis

Skills

ASIC implementation

Synthesis

STA

Physical design

EMIR analysis tools

Power integrity

Scripting

Education

BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS

Tools

Redhawk-SC

Voltus

FusionCompiler

Innovus

PrimePower

PrimeTime

Job description

Amazon is seeking a Sr. EMIR Engineer to join the MLA team in Cupertino, CA. You will define EMIR sign‑off for Inf/Trainium SoCs, model demand currents, and collaborate with architects, designers and power/thermal experts to ensure robust IR and power integrity across die, package and board levels.

You will design and run EMIR analyses, develop vectors, dashboards, and best practices, and partner with EDA vendors to advance methodologies. A strong background in ASIC power integrity is essential.