Senior Signoff CAD Engineer - SoC Power/EMIR, AI-Driven

Apple Inc.; Austin (TX); On-site; USD 160,000 - 230,000; Full time

Job summary

Apple Inc. in Austin, TX seeks a Senior Signoff Engineer to define and execute signoff across gate and transistor levels for next‑generation mixed-signal SoCs. You will collaborate with Design, CAD, and Technology teams to ensure robust power/EMIR verification and drive AI/ML enhancements to signoff flows.

The role emphasizes hands-on analysis, scripting proficiency in Python/Perl, and strong communication to enable rapid debug and reliable tapeout.

Qualifications

• BS + 10+ years of relevant industry experience.
• Experience in CAD, EMIR analysis.
• Knowledge of transistor and gate-level EMIR analysis across static and dynamic modes.
• Experience applying AI/ML or LLM-based tools to EDA flow automation.

Responsibilities

• Define signoff requirements early in the project lifecycle.
• Lead signoff for functional static/dynamic IR analysis, scan-mode IVD, and power EM analysis.
• Collaborate with Design, CAD, and Technology teams to ensure correct EDA flows.
• Provide frontline support for enablement, enhancement, and debugging requests.

Skills

Signoff engineering

EMIR analysis

Python

Perl

CMOS analog

AI in EDA

Education

BS in EE

Tools

Redhawk

Voltus

Totem

Job description

Apple Inc. in Austin, TX seeks a Senior Signoff Engineer to define and execute signoff across gate and transistor levels for next‑generation mixed-signal SoCs. You will collaborate with Design, CAD, and Technology teams to ensure robust power/EMIR verification and drive AI/ML enhancements to signoff flows.

The role emphasizes hands-on analysis, scripting proficiency in Python/Perl, and strong communication to enable rapid debug and reliable tapeout.