CAD EMIR Signoff Engineer

Pentangle Tech Services | P5 Group; Irvine (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

Pentangle Tech Services | P5 Group seeks a senior EMIR power analyst to develop and support block and top-level power analysis flows for Samsung GPU IP. You will tackle static and dynamic IR drop, vector-less analysis, EMIR, and effective resistance, interfacing with CAD teams and EDA vendors.

Strong Tcl/Python skills, Verilog/DEF familiarity, and a track record of successful tape-outs are essential for this role based in Irvine, CA.

Qualifications

• 5+ years EMIR experience in SOC/ASIC/GPU/CPU design flows.
• Tape-out track record and experience with power integrity flows.
• Strong scripting in Tcl, Shell, Python; read/write Verilog/DEF.
• Experience with 16nm FinFET or smaller process nodes.

Responsibilities

• Develop and support static, vector-less IR drop analysis solutions.
• Develop and support dynamic IR drop analysis for vector and vector-less cases.
• Develop and support signal electro-migration analysis solutions.
• Develop and support effective resistance analysis solutions.
• Collaborate with EDA vendors, power network planners, and design leads to meet milestones.
• Participate in CAD, signoff flows, power network creation in top/block environments.

Skills

EMIR analysis

Tcl scripting

Python scripting

Verilog

DEF

Block-level design

Full-chip implementation

P&R/STA flows

16nm FinFET

Cross-functional collaboration

Education

BSEE / Computer Engineer

Tools

P&R/STA tools

Verilog/DEF reading

Job description

Role And Responsibilities

This is a senior level position where the candidate will develop and support block and top level power analysis flows (EMIR) in the development of Samsung state of the art GPU IP. The candidate is tasked with supporting static power analysis, transient vector and vector-less dynamic power analysis, signal electro-migration analysis and effective resistance analysis. Significant experience in understanding switching activity propagation, current density calculations and knowledge of industry standard power analysis tools are critical for the candidate. Strong background in programming tcl and python are necessary to develop and support flows, scripts and tools that operate in these analysis domains.

Key Responsibilities Include

• Develop and support static, vector-less IR drop analysis solutions
• Develop and support dynamic IR drop analysis solutions for both vector and vector-less cases
• Develop and support signal electro-migration analysis solutions
• Develop and support effective resistance analysis solutions
• Heavy interaction with EDA tool vendors, power network planners, block owners and design leads to ensure execution of project milestones
• Participate in CAD, signoff flows, power network creation and both top and block design environments

Skills And Qualifications

Minimum requirements:

• BSEE, Computer Engineer or comparable with at least 5+ years of direct relevant EMIR experience
• Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with experience in taping out designs
• Hands-on experience with block and full chip implementation with the latest industry P&R/STA flows and tools
• Experience in block level floor-planning, power grid implementation and EMIR based experience both early and late in project cycle
• Strong scripting/programming skills in Tcl, Shell, and Python
• Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
• Be in a EMIR design or CAD role with a successful tape out track record is required
• Strong communication skills, proven track record of a physical design lead, ability to influence and work with cross functional teams to achieve milestones and project targets, discipline and planning; ability to execute with high quality deliverables is a must
• Experience with 16nm Finfet or smaller process nodes
• Experience with design implementation of GPU/CPU/SOC tiles and full-chip implementation work with standard industry standard tools is advantageous
• Ability to read/use Verilog and DEF is preferred with good interaction with physical implementation teams
• Strong programming skills with tcl and python for the creation of analysis support scripts and tool support