Senior SoC Power Engineer for Cloud-Scale ML

Amazon Inc.; Cupertino (CA); Hybride; USD 213 000 - 288 000; Plein temps

Avantages offerts par ce poste

Health insurance

401(k) matching

Paid time off

Parental leave

Résumé du poste

Amazon Inc. in Cupertino is seeking a Sr. SoC Power Engineer to model and estimate power from RTL to final netlist and drive power reduction for our MLA accelerators.

You will collaborate with architects, designers, verification and Physical Design teams to define best practices and achieve high-accuracy power estimates. The role requires deep circuit-level power knowledge, expertise with power analysis tools, and strong scripting skills.

Qualifications

• Bachelor's degree in EE/CS or related field.
• BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS.
• Expert on power analysis tools like PrimePower, PowerArtist.
• Deep circuit-level understanding of chip power.
• Ability to give feedback to RTL designers and Physical Designers on how to reduce power.
• Proficient in scripting (Tcl, Perl, Python).
• Knowledge of Physical Design, EM/IR, Power Integrity, and Thermal.
• Experience with lab power analysis.

Responsabilités

• Perform full chip power analysis & modelling RTL to gate level netlist.
• Develop and maintain dashboards for power rollups.
• Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation.
• Give feedback to designers and architects on how to reduce power.
• Make power measurements in the lab and correlate back to simulations.
• Work with Emulation engineers to model chip-level power consumption.

Connaissances

Power analysis tools

Circuit-level power

Scripting (Tcl/Perl/Python)

Physical Design awareness

Lab power analysis

Formation

Bachelor's degree in EE/CS

Master's degree in EE/CE/CS (preferred)

Outils

PrimePower

PowerArtist

Redhawk

Voltus

Zebu Emulator

Description du poste

Amazon Inc. in Cupertino is seeking a Sr. SoC Power Engineer to model and estimate power from RTL to final netlist and drive power reduction for our MLA accelerators.

You will collaborate with architects, designers, verification and Physical Design teams to define best practices and achieve high-accuracy power estimates. The role requires deep circuit-level power knowledge, expertise with power analysis tools, and strong scripting skills.