Senior DV Engineer — SoC Verification (ARM/AXI, Onsite CA)

Quest Global; San Jose (CA); On-site; USD 103,000 - 124,000; Full time

Job summary

Quest Global seeks a Senior DV Engineer to lead end-to-end design verification for IP, subsystem, or SoC projects. You will work with design, architecture and customer teams to achieve verification closure with high quality.

The role requires HVL expertise (UVM/SystemVerilog/OVM), C/C++, and experience with ARM cores, DSPs, DDR3, and interconnects. Onsite in San Jose, CA with global collaboration.

Qualifications

• BE/BTech/MTech in Electronics, Electrical, or related disciplines.
• Strong in HVL (UVM / SystemVerilog / OVM) and C/C++/Perl/TCL.
• Experience with constraint random verification and coverage analysis.

Responsibilities

• Lead end-to-end design verification for IP, subsystem or SoC projects.
• Collaborate with design, architecture and customer teams to close verification.
• Verify SOCs with embedded ARM CPUs, DSPs, DDR3 and interconnects.
• Work with HVL, UVM, assertions, and coverage to ensure quality.

Skills

UVM/SystemVerilog

C/C++

Perl/Tcl scripting

Constraint random verification

Assertion writing

ARM cores familiarity

Education

BE/BTech/MTech in Electronics/EE

Tools

EDA tools

FPGA prototyping

Job description

Quest Global seeks a Senior DV Engineer to lead end-to-end design verification for IP, subsystem, or SoC projects. You will work with design, architecture and customer teams to achieve verification closure with high quality.

The role requires HVL expertise (UVM/SystemVerilog/OVM), C/C++, and experience with ARM cores, DSPs, DDR3, and interconnects. Onsite in San Jose, CA with global collaboration.